1. Field of the Invention
The present invention relates generally to a semiconductor memory device of a redundant circuit system, and a method for producing the same.
2. Description of the Related Art
Semiconductor memory devices, particularly DRAMS, are scaled down and large-scale-integrated year by year. With such scale down and large scale integration, it become more and more difficult to hold the same yield as those of the last generation DRAMs. Therefore, in recent years, there is adopted a redundant circuit system for arranging a redundant cell array (an auxiliary cell array) for a memory array to substitute a redundant cell for a defective cell to carry out defect relief.
In a conventional redundant circuit technique, a fuse circuit capable of being cut (blown) by a laser is typically used as a defective address memory circuit. Specifically, a defective cell is identified by carrying out the die sort in the stage of a semiconductor wafer, on which a plurality of DRAM circuits have been integrated. On the basis of the defective address data, a corresponding fuse is cut by a laser blowing machine. Thereafter, the wafer is divided into DRAM chips, each of which is sealed in a package to carry out the final inspection thereof.
In the conventional redundant circuit technique using the laser blow, there are the following problems. First, if the scale of the DRAM increases by four, the scale of the fuse circuit for storing the defective address also increases by four, so that the throughput of the laser blow decreases to one-fourth. Secondly, since the pitch of the fuse array is determined by the capacity of the laser blowing machine, even if the DRAM has a fine design rule of 0.25 to 0.35 .mu.m, the pitch of the fuse array can not be 3 to 4 .mu.m or less. This means that the area occupied by the fuse array in the DRAM chip relatively increases every DRAM generation.
As a fuse element of a semiconductor integrated circuit other than the fuse element of the system capable of being cut by the laser blow, there are also known systems using an electric fuse capable of being electrically cut or short-circuited (e.g., see Japanese Patent Laid-Open No. 6-5707 and No. 6-302701), and a system using a mechanical fuse capable of being cut by etching (e.g., Japanese Patent Laid-Open No. 1-308047). If these fuses are used, the fuse array can be scaled down.
However, in a case where the electric fuse is used, if the scale of the fuse array becomes large, the scale of surrounding circuits, such as a signal generating circuit required for programming the fuse array, also becomes large. Therefore, there is some possibility that the area occupied by the defective address memory circuit including the fuse array and the surrounding circuits thereof is substantially equal to that when the fuse of the laser blow system is used. In addition, in a case where the mechanical fuse capable of being cut by etching is used, a programming step is carried out at least before a passivation step for a semiconductor wafer is completed, so that it is not possible to relieve a defective cell when the defective cell is produced at the subsequent step.